The present invention relates to an LSI design method, and, in particular, relates to a technique which is effective for suppressing power consumption due to a clock tree.
For a logic LSI, there is typically used synchronous design providing a clock tree from a clock generation source to a flip-flop (hereinafter, abbreviated as FF) which is operated in synchronization with a clock therefrom. A combination circuit exists between the FFs and a timing specification such as a set-up time and a hold time is defined by a relationship among a clock skew, a signal propagation delay by the combination circuit, and a clock period. The clock skew represents a time difference when the clocks arrive at one pair of FFs, which are a start point and an end point of signal propagation, from the clock generation source. When the start point FF shifts output level in synchronization with the clock, the logic operation result arrives at the endpoint FF having a signal propagation delay by the combination circuit. The arrival timing needs a certain degree of margin for the clock period, and the margin is referred to as the set-up time. Further, the hold time is defined for preventing a problem referred to as racing that the signal propagation delay is too small and the signal level shift at the start point appears in the output of the end point within the same clock period.
Such an LSI design method generally includes the steps of Logic Synthesis, Clock Tree Synthesis (CTS), placement and routing, timing analysis, and verification.
In the Logic Synthesis, a logic circuit is synthesized at a gate level from an input of a logic which is designed by a designer in a format of high-level logic description. The logic circuit is synthesized typically by synchronous design which provides a clock tree from a clock generation source to FFs which are operated in synchronization with a clock therefrom. The FFs are disposed at a start point and an end point of signal propagation delay by a combination circuit and configure timing definition circuits in the synchronous design. When the FF which is the timing definition circuit at the start point shifts output level in synchronization with the clock, the logic operation result arrives at the FF which is the timing definition circuit at the end point, through a signal propagation delay by the combination circuit. The arrival timing needs a certain degree of margin for the clock period and the margin is referred to as a set-up time. Meanwhile, a hold time is defined for preventing a problem referred to as racing that the signal propagation delay is too small and the signal level shift at the start point appears in the output of the end point within the same clock period. The timing definition circuit includes not only the FF but also a latch circuit, a clock-synchronous type memory, a gate circuit which controls clock gating, and the like.
In the Clock Tree Synthesis (CTS), clock buffers are configured to form a tree shape so as to supply the clock from the clock generation source to all the timing definition circuits such as the FFs. For supplying the clocks from one clock generation source to many timing definition circuits, the number of supply targets is increased through a plurality of times of branching. One or a plurality of buffers is provided in series in each of a plurality of branches extended from a branch point and further coupled to the next branch point. In the synchronous design, generally, the design is performed so that the clock arrives at all the timing definition circuit at the same time. This is because the Logic Synthesis is carried out on the premise of the above requirement. An error of time when the clock arrives at the timing definition circuit is referred to as a skew.
The placement and routing determines an arrangement of cells corresponding to respective gates of the logic circuit and performs routing between the cells. As a result, LSI layout information is generated.
The timing analysis includes dynamic timing analysis of performing transient analysis and Static Timing Analysis (STA) which extracts a load capacitance and a wiring resistance of a wiring, thereby calculates a delay time for each gate and performs the timing analysis by addition and subtraction of the delay times, without performing the transient analysis. The STA, which requires a small operation amount, is employed typically in LSI design for a large circuit scale. The STA calculates a signal propagation delay from the clock generation source to the timing definition circuit of the start point or the endpoint by accumulating the delays of the clock buffers, calculates a signal propagation delay by a combination circuit between the start point and the end point, and calculates margins to the set-up time and the hold time. The margin for the set-up time is referred to as a slack, and the slack is expressed to be negative when violation occurs and expressed to be positive when a margin exists. The STA calculates all the margins to the set-up time and the hold time for all the combination circuits having the start points and the end points at all the timing definition circuits. When the STA is performed after the placement and routing, a parameter affecting the delay such as the load capacitance and the wiring resistance is extracted from the layout information and the delay can be calculated more accurately.
The verification includes Design Rule Check (DRC) and circuit layout verification (LVS; Layout vs. Schematic), and performs verification of various kinds of rules in the layout information and agreement verification between a layout and a circuit diagram.
In contrast, reduction of power consumption in a logic LSI is a subject which has become more and more important and, in particular, it is extremely important to reduce power consumption of a clock system represented by the clock tree. Although the circuit scale of the clock tree is smaller than that of the combination circuit, since state transition probability per unit time of the clock is several times higher than that of data, the power consumption of the clock tree occupies a comparatively high ratio in the logic LSI. Accordingly, suppression of the power consumption in the clock tree contributes greatly to the reduction of the power consumption in the whole logic LSI.
Patent Document 1 (Japanese Patent Laid-Open No. 2006-031141) discloses a technique of adjusting the arrival time of the clock at the FF for resolving the set-up violation. This is a technique of eliminating the worst slack in the set-up violations by adding or removing the clock buffer in the clock tree.
Patent Document 2 (Japanese Patent Laid-Open No 2002-108962) discloses a flow optimizing a clock line for resolving the set-up violation. The FF at the end point of a set-up violation path is replaced by the FF provided with a delay for delaying the clock.
Patent Document 3 (Japanese Patent Laid-Open No 2006-319162) discloses a clock tree generation method which can perform reduction of the power consumption and improvement of a set-up/hold error. This is a technique of reducing the power consumption by reducing the number of delay elements on the clock tree and resolving the error by re-arranging cells configuring a path where the set-up/hold error is caused and by reducing wiring lengths. Clock load cells (typically, FF) are re-arranged so as to cause the wiring length from the clock generation source to the clock load cell to fall within a predetermined range, and thus the number of buffers on the clock tree is reduced to a minimum to be required and the set-up/hold error is resolved at the same time.